In recent years the size of ICs has dramatically increased in both physical size and number of logical components. This has resulted in multiple clocks activating the logical components. In typical IC designs, a clock domain is defined as a set of all logical components (e.g., flip-flops, registers, synchronous RAM, and so on) that are clocked on the same edge of the same clock net. Clock domains that exchange data, also referred to as “clock-domain crossing” needed to be interfaced and synchronized in reliable and predictable ways to ensure the proper transfer of data from one clock domain to another.
In the related art, there are several techniques for avoiding asynchronous clock-domain crossing and to reduce the probability of meta-stability. These techniques are based on adding a combinational logic which interfaces between the two time domains.
Reference is now to FIG. 1 where a logic circuit 100 including two clock domains 120 and 140, is shown. The first clock domain 120 includes a register 122 clocked by a first clock signal “Clk1”. The second clock domain 140 includes a register 142 clocked by a second clock signal “Clk2”. It will be appreciated herein that the term, “register” as used in this description has a special meaning, and is not limited to just a register. Instead, the term “register” means any logic component for holding data, such as any type of flip-flop, memory cell, or combinational logic loops that form a de facto memory, and the like. Thus, “register” as used herein is just a convenient shorthand notation for the foregoing equivalents, and any similar device or combination of devices for performing this memory function.
Logical circuit 100 further includes a synchronization cell 130 which interfaces between the first clock domain 120 and the second clock domain 140. Synchronization cell 130 may include combinational logic circuit including registers, multiplexers (MUXs), sequential logical, or combinations thereof. Typically, synchronization cell 130 is a simple logic, such as a double-level register or a recirculation MUX double-registered control. However, in some cases, more complex circuits may be utilized for synchronization cell 130, for example, a handshaking mechanism which may be a complex sequential circuit. Essentially, synchronization cell 130 is designed to prevent register 142 from sampling data, while register 122 is changing the data.
Clock synchronization validation in clock-crossing domains is one of the most important and difficult tasks in verification of large ICs. In the related art, analysis tools are used for verification of clock-domain crossing early in the design process. The verification is performed by identifying synchronization cells in the design. Simple synchronization cells, such as a double-level register and a recirculation MUX, can be easily verified by exploring the structure of the IC's design. This verifying process is usually referred to as “structurally verifiable”. On the other hand, complex synchronization cells, such as a handshake mechanism, can be verified using advanced functional analysis. This verifying process is usually referred to as “functionally verifiable”. In both cases, prior art analysis tools require the user's intervention in specifying a different set of data and a different type of test. Moreover, such tools generally identify all asynchronous clock domains that are not structurally verifiable as invalid asynchronous clock domains, even if those clock domains are well synchronized. This requires the designer to spend significant time in verifying each asynchronous clock domain separately. In typical ICs, where the number of clock-domain crossing may be large, this is an inefficient and a time-consuming task as well as being error prone.
Therefore, in the view of the limitations introduced in the prior art, it would be advantageous to provide an efficient solution that would verify the validity of clock-crossing domains in the absence of explicit synchronization cells. It would be further advantageous if the provided solution would identify functionally verifiable circuits without the user intervention.